Soitec - Model FD-2D - Next Generation Performance with Current Technology
From Digital SOI
As it’s getting harder and harder to make strides towards energy efficiency and high performance in a cost-effective way, innovative Soitec FD-2D wafers provide an early and low-risk path to continue the pace of technology advancement, now for 28 nm down to 14 nm.
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Soitec FD-2D substrates offer atomic-level uniform...
Soitec FD-2D substrates offer atomic-level uniformity required to implement planar fully depleted CMOS technology. We can supply standard and customer-specific structures. We draw upon our proven manufacturing track record to fabricate our FD-2D product line to the highest standards in terms of quality, yield and productivity.
Uniformity of the top silicon layer of Soitec FD-2D wafers is guaranteed to within +/-5Å at all points on all wafers. This uniformity is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. For planar fully depleted SOI (FDSOI) CMOS technology, uniform thickness is crucial to controlling transistor Vt variations. Soitec’s ability to comply with this specification, even for high-volume production runs, opens the door to industrial rollout of FDSOI as a practical way to perpetuate Moore’s Law at the 28 nm node—and beyond. FDSOI is design friendly and cost efficient, and enables better performance and higher energy efficiency.
All Soitec FD-2D substrates are made using our proven Smart Cut™ technology and Soitec’s years of experience producing SOI wafers in high-volume manufacturing environments. We use thermal-oxide growth and implantation to control SOI thickness uniformity.
Benefits
Benefits
Soitec FD-2D is an extremely attractive option for those looking for cost-efficiency, high performance and very low power consumption at advanced nodes for the consumer market. Soitec FD-2D brings end-users a balanced combination of:
- Fast time-to-market by enabling 28 nm planar fully depleted technology now with scalability down to 14 nm:
- FD-2D enables fully depleted transistors with the convenience of planar technology
- Same design methodologies and reuse of legacy intellectual property blocks
- Smooth evolution from planar bulk CMOS processing with similar fab tools and process steps
- Better performance and longer battery life compared to both low-power and performance-oriented flavors of traditional bulk CMOS:
- Power savings as much as 40% at the same overall performance level and peak performance boosted by 40% for the same power consumption
- Performance at low power supply (e.g., 0.7 V) improved by over x2
- Substantially reduced variability and short channel effects
- Cost-effective final product :
- Significantly reduced number of process steps
- Full compatibility with planar CMOS production lines
- Extremely competitive total cost of ownership
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